R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 239

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.5.4
A data TLB multiple hit exception occurs when more than one UTLB entry matches the virtual
address to which a data access has been made.
When a data TLB multiple hit exception occurs, a reset is executed, and cache coherency is not
guaranteed. The contents of PPN in the UTLB prior to the exception may also be corrupted.
Hardware Processing: In the event of a data TLB multiple hit exception, hardware carries out the
following processing:
1. Sets the virtual address at which the exception occurred in TEA.
2. Sets exception code H'140 in EXPEVT.
3. Branches to the reset handling routine (H'A000 0000).
Software Processing (Reset Routine): The UTLB entries which caused the multiple hit
exception are checked in the reset handling routine. This exception is intended for use in program
debugging, and should not normally be generated.
6.5.5
A data TLB miss exception occurs when address translation information for the virtual address to
which a data access is made is not found in the UTLB entries. The data TLB miss exception
processing carried out by hardware and software is shown below.
Hardware Processing: In the event of a data TLB miss exception, hardware carries out the
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'040 in the case of a read, or H'060 in the case of a write in EXPEVT
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
(OCBP, OCBWB: read; OCBI, MOVCA.L: write).
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
saved in SGR.
Data TLB Multiple Hit Exception
Data TLB Miss Exception
Section 6 Memory Management Unit (MMU)
Rev. 2.00 May 22, 2009 Page 169 of 1982
REJ09B0256-0200