R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 674

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
• Burst Mode (LCKN = 0, TB = 1)
Figure 14.9 shows DMA transfer timing in burst mode.
(3)
Table 14.10 shows the DMA transfer matrix in auto-request mode and table 14.11 shows the
DMA transfer matrix in external request mode, and table 14.12 shows the on-chip peripheral
module request.
Rev. 2.00 May 22, 2009 Page 604 of 1982
REJ09B0256-0200
In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is
performed continuously without releasing the bus mastership until the transfer end condition is
satisfied. In external request mode with level detection of the DREQ pin, however, when the
DREQ pin is not active, the bus mastership passes to the other bus master after the DMAC
transfer request that has already been accepted ends, even if the transfer end conditions have
not been satisfied.
Burst mode cannot be used when the on-chip peripheral module is the transfer request source.
DMA Transfer Matrix
DREQ
SuperHyway
bus cycle
Figure 14.9 DMA Transfer Timing Example in Burst Mode
CPU
CPU
(DREQ Low Level Detection)
CPU
DMAC DMAC DMAC
Read
Write
Read
DMAC DMAC
Write
Read
DMAC
Write
CPU