R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 366

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
and determines the priorities of individual interrupt sources. The lowest one bit is then rounded
off, the data is converted to 4-bit data, and the priority levels are notified. For example, two
interrupt sources whose priority levels are set to H'1A and H'1B are both output as 4-bit priority
level H'D. That is, the two interrupt sources have the same value. However, in terms of the
INTEVT code that is notified when a conflict occurs between two interrupt sources, the INTEVT
code that corresponds to the interrupt with a priority level of H'1B has priority. This is because the
priority level of H'1B is higher than that of H'1A when comparing 5-bit data. When a conflict
occurs between interrupts with the same priority level, the INTEVT code is notified according to
the priority level shown in table 9.1.
INTC
Priority level: high (H'1B)
9.4.6
Table 9.7 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority.
Each interrupt source is assigned a unique INTEVT code. The start address of the exception
handling routine is common to each interrupt source. Therefore, to identify the interrupt source,
branching is performed at the start of the exception handling routine using the INTEVT value. For
instance, the INTEVT value is used as a branch offset.
Rev. 2.00 May 22, 2009 Page 296 of 1982
REJ09B0256-0200
CPU
Priority level:
When multiple interrupt from on-chip modules
occur simultaneously, the INTC proesses the priority level
H'1B is higher than that of H'1A.
However, if an external interrupt will be higher priority in some
case.
INTC can distinguish H'1A from H'1B on-chip module
interrupt priority level that same for the CPU.
NMI interrupt request
IRQ or IRL interrupt request that the same priority
level or more (H'D or more in this figure).
Interrupt Exception Handling and Priority
0
0
0
0
0
0
0
0
Figure 9.3 On-chip Module Interrupt Priority
even (H'D)
1
low (H'1A)
1
1
1
1
0
0
1
1
0
Priority level H'01 is same with interrupt request mask.
INTC
Priority level: H'01
CPU
Priority level: H'0 (interrupt is masked)
Priority level H'01 becomes H'00 by rounding off the lowest
bit, and then interrupt is not notifited to the CPU. The
setting rauge of the interrupt priority register is H'02 to H'1F
(30 priority levels).
0
0
0
0
0
0
0
0
1