R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1111

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Note:
Bit
3
2
1
0
*
This bit can be read from or written to. Writing 0 clears this bit to 0 and writing 1 is
ignored.
Bit Name
MDE
MDT
MDR
MAT
Initial Value
0
0
0
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Master Data Empty
At the start of a byte data byte transmission,
the contents of the transmit data register are
loaded into a shift register ready for
transmitting on the bus. When this bit is set to
1, it indicates that the transmit data register is
available for further data by setting this
register.
During master transmit mode, the MDE bit is
set at the same timing as the MAT bit is also
set after transmission of the slave address. In
this case, you need to set the MDT and MAT
bits after the ICMCR's ESG bit is cleared. The
clearing will restart the data transmission.
Master Data Transmitted
Byte data has been sent to the slave on the
bus. This status bit becomes active after the
falling edge of SCL during the last data bit.
Master Data Received
Byte data has been received from the bus and
is in the receive data register. This status bit
becomes active after the falling edge of SCL
during the last data bit. During single-buffer
mode, this status bit must be reset after data
has been read from the receive data register.
When MDBS is set to 1, SCL will be held low
from the timing when the receive data register
acquires the data packet until the MDR flag is
cleared.
During master reception mode, the MDR bit is
set at the same timing as the MAT bit set after
transmission of the salve address. In this case,
you must clear the MDR and MAT bits after the
ICMCR's ESG bit is cleared. Clearing will start
the data reception
Master Address Transmitted
The master has been transmitted the slave
address byte of a data packet. This bit
becomes active after the falling edge of SCL
during the ack bit of after the address.
Rev. 2.00 May 22, 2009 Page 1041 of 1982
Section 26 I
2
C Bus Interface (IIC)
REJ09B0256-0200