R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 415

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
9, 8
7
6 to 4
Bit Name
SZ
RDSPL
BW
Initial
Value
11
0
111
R/W
R/W*
R/W
R/W
Description
Bus Width
Specify the bus width. In CS0BCR, the external pins
(MD3 and MD4) are sampled at a power-on reset. Set
to 11 for the MPX interface, and set to 10 or 11 for the
byte control SRAM interface.
00: Reserved
01: 8 bits
10: 16 bits
11: 32 bits
Note: * Bits SZ in CS0BCR are read-only. The SZ bits
RD Hold Cycle
Specify the number of cycles to be inserted into the RD
assertion period to ensure the data hold time to the
read data sample timing. When set this bit to 1, specify
the number of RD negation-CSn negation delay cycle to
be 1 or more by setting the RDH bit in CSnWCR. And
RD negation-CSn negation delay cycle is reduced 1
cycle to set this bit to 1 (Available only when the SRAM
interface or byte control SRAM interface).
0: No hold cycle inserted
1: 1 hold cycle inserted
Burst Pitch
When the burst ROM interface is used, these bits
specify the number of wait cycles to be inserted after
the second data access in a burst transfer.
000: No idle cycle inserted, RDY signal disabled
001: 1 idle cycle inserted, RDY signal enabled
010: 2 idle cycles inserted, RDY signal enabled
011: 3 idle cycles inserted, RDY signal enabled
100: 4 idle cycles inserted, RDY signal enabled
101: 5 idle cycles inserted, RDY signal enabled
110: 6 idle cycles inserted, RDY signal enabled
111: 7 idle cycles inserted, RDY signal enabled
in CS0BCR are set to 11 when area 0 is set to
MPX interface by the MD3 and MD4 pins.
Section 11 Local Bus State Controller (LBSC)
Rev. 2.00 May 22, 2009 Page 345 of 1982
REJ09B0256-0200