R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1147

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
4
3
2
Bit Name
RE
REIE
—
Initial
Value
0
0
0
R/W
R/W
R/W
R
Description
Receive Enable
Enables or disables the start of serial reception by the
SCIF.
Serial reception is started when a start bit is detected in
this state in asynchronous mode or a synchronization
clock is input while the RE bit is set to 1.
It should be noted that clearing the RE bit to 0 does not
affect the DR, ER, BRK, RDF, FER, PER, and ORER
flags, which retain their states. Serial reception begins
once the start bit is detected in these states.
0: Reception disabled
1: Reception enabled*
Note: * SCSMR and SCFCR settings must be made,
Receive Error Interrupt Enable
Enables or disables generation of receive-error
interrupt (ERI) and break interrupt (BRI) requests. The
REIE bit setting is valid only when the RIE bit is 0.
Receive-error interrupt (ERI) and break interrupt (BRI)
requests can be cleared by reading 1 from the ER,
BRK, or ORER flag, then clearing the flag to 0, or by
clearing the RIE and REIE bits to 0. When REIE is set
to 1, ERI and BRI interrupt requests will be generated
even if RIE is cleared to 0. In DMAC transfer, this
setting is made if the interrupt controller is to be notified
of ERI and BRI interrupt requests.
0: Receive-error interrupt (ERI) and break interrupt
1: Receive-error interrupt (ERI) and break interrupt
Reserved
This bit is always read as 0. The write value should
always be 0.
Section 27 Serial Communication Interface with FIFO (SCIF)
(BRI) requests disabled
(BRI) requests enabled
the reception format decided, and the receive
FIFO reset, before the RE bit is set to 1.
Rev. 2.00 May 22, 2009 Page 1077 of 1982
REJ09B0256-0200