R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 235

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.5
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB and instruction
cache because data is only read in these cases. In this LSI, entry specification is performed using
bits 12 to 5 of the virtual address in order to achieve fast operand cache operation. However, bits
12 to 10 of the virtual address in the case of a 1-Kbyte page, and bit 12 of the virtual address in the
case of a 4-Kbyte page, are subject to address translation. As a result, bits 12 to 10 of the physical
address after translation may differ from bits 12 to 10 of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
• When address translation information whereby a number of 1-Kbyte page UTLB entries are
• When address translation information whereby a number of 4-Kbyte page UTLB entries are
• Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
• Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12:10]
values are the same.
translated into the same physical address is recorded in the UTLB, ensure that the VPN[12]
value is the same.
page size.
page size.
provide for future expansion of the SuperH RISC engine family, ensure that the
VPN[20:10] values are the same. Also, do not use the same physical address for address
translation information of different page sizes.
Avoiding Synonym Problems
Section 6 Memory Management Unit (MMU)
Rev. 2.00 May 22, 2009 Page 165 of 1982
REJ09B0256-0200