R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1286

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 29 Serial I/O with FIFO (SIOF)
29.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame.
Rev. 2.00 May 22, 2009 Page 1216 of 1982
REJ09B0256-0200
Initial value:
Bit
5, 4
3 to 0
Bit
15
14 to 12 —
11 to 8
R/W:
BIt:
Bit Name
—
TDRA[3:0]
Bit Name
RDLE
RDLA[3:0]
RDLE
R/W
15
0
14
—
R
0
13
—
R
0
Initial
Value
All 0
0000
Initial
Value
0
All 0
0000
12
—
R
0
R/W
R/W
R/W
R
R/W
R/W
R
R/W
11
0
R/W
RDLA[3:0]
10
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmit Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Description
Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
Reserved
These bits are always read as 0. The write value
should always be 0.
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
R/W
9
0
Transmit data for the right channel is specified in
the SITDR bit in SITDR.
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
R/W
8
0
RDRE
R/W
7
0
—
R
6
0
—
R
5
0
—
R
4
0
R/W
3
0
RDRA[3:0]
R/W
2
0
R/W
1
0
R/W
0
0