R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1162

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 27 Serial Communication Interface with FIFO (SCIF)
27.3.13 Line Status Register (SCLSR)
Notes: 1. Only 0 can be written, to clear the flag.
Rev. 2.00 May 22, 2009 Page 1092 of 1982
REJ09B0256-0200
Initial value:
Bit
15 to 1
0
R/W:
BIt:
2. The ORER flag is not affected and retains its previous state when the RE bit in SCSCR
3. The receive data prior to the overrun error is retained in SCFRDR, and the data
Note: * Only 0 can be written, to clear the flag.
Bit Name
ORER
is cleared to 0.
received subsequently is lost. Serial reception cannot be continued while the ORER flag
is set to 1.
15
R
0
14
R
0
13
R
0
Initial
Value
All 0
0
12
R
0
11
R
0
R/W
R
R/W*
10
R
0
1
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Overrun Error
Indicates that an overrun error occurred during
reception, causing abnormal termination.
0: Reception in progress, or reception has ended
[Clearing conditions]
1: An overrun error occurred during reception*
[Setting condition]
normally*
R
9
0
Power-on reset or manual reset
When 0 is written to ORER after reading ORER = 1
When the next serial reception is completed while
SCFRDR receives 64-byte data (SCFRDR is full)
R
8
0
2
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
3
R
1
0
ORER
R/W*
0
0

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