R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1018

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
frame can be stored in buffer 1 (set RBL to 14 bytes) and the remaining data can be stored in
buffer 2 (set RBL to 1500 bytes). All receive frames, of course, can be stored in a single buffer if
multiple descriptors are prepared and RBL of each descriptor is set to more than 1514 bytes
(maximum Ethernet frame length).
(a)
The user sets whether the bits of the descriptor are valid or invalid and whether the descriptor
represents the end of the descriptor list in RD0 before the RR bit in EDRRR is set to 1 and the
start of a read by the E-DMAC. After receive DMA transfer of an Ethernet frame by the E-
DMAC, the E-DMAC disables the valid/invalid bits of the descriptor and writes status
information. This operation is referred to as write-back.
When using RD0, the user should write desired values to bits 31 and 30 according to the
descriptor configuration. Bits 29 to 0 should be cleared to 0.
Rev. 2.00 May 22, 2009 Page 948 of 1982
REJ09B0256-0200
Note: *According to the descripotr lenght set by the DL0 and DL 1 bits in EDMR, the padding size is detemined as follows:
Receive Descriptor 0 (RD0)
For 16 bytes Padding = 4 bytes
For 32 bytes padding = 20bytes
For 64 bytes Padding = 52bytes
RD0
RD1
RD2
Figure 23.4 Relationship between Receive Descriptor and Receive Buffer
Receive deschriptor
31
R
A
C
T
31
31
30
R
D
L
E
29 28
R
F
P
RBL
27
R
F
E
26
P
V
Padding (4/20/52 bytes)*
25
Reserved
16
RBA
15
12 11
TFS[26:0]
0
0
0
Transmit buffer
Valid transmit data