R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 379

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9.7
9.7.1
If an interrupt request is accepted when level-sensed IRQ or level-encoded IRL interrupt request is
selected, the held request must be cleared in the interrupt handling routine. Figure 9.5 shows an
example of clearing the interrupt request held in the detection circuit.
After the CPU accepts an interrupt request, acceptance of the request should be notified to the
external devices and the request should be cancelled. For example, acceptance can be notified by
outputting the accepted level and pin-related information via the GPIO (general I/O port) and
writing the acceptance information to a specific address in the local bus space. Here, writing to the
GPIO register or local bus space and reading from the location should be consecutively executed.
When clearing the interrupt requests held in the detection circuit, adequate time is necessary for
the CPU to detect the cancellation of the interrupt request. To secure the time, writing to
Usage Notes
Example of Interrupt Handling Routine for Level-Encoded IRL and Level-Sensed
IRQ
Clear the level-encoded IRL or level-sensed IRQ interrupt
An appropriate time is necessary for the interrupt request
input to the IRQ/IRL pin to be cancelled and for the INTC
to detect the cancellation (more than 8 bus clock cycles).
Set the corresponding mask bit to 1 to clear the interrupt
Start of level-encoded IRL or level-sensed IRQ interrupt
Notify acceptance of the interrupt to external devices by
End of level-encoded IRL or level-sensed IRQ interrupt
Clear the interrupt request held in the detection circuit.
Wait for the level-encoded IRL or level-sensed IRQ
Figure 9.5 Example of Interrupt Handling Routine
using GPIO output or local bus space.
request held in the detection circuit.
interrupt request to be cleared.
Interrupt handing
request source.
handing
handing
Rev. 2.00 May 22, 2009 Page 309 of 1982
1. Write to the GPIO register or
2. Read the address to which
1. Set the corresponding bit in
2. Set the corresponding bit in
3. Read INTMSK0/INTMSK1.
local bus space.
writing has been made.
INTMSK0/INTMSK1.
INTMSKCLR0/INTMSKCLR1.
Section 9 Interrupt Controller (INTC)
REJ09B0256-0200