R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1856
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 41 User Break Controller (UBC)
41.3.3
1. If the instruction fetch cycle is set in the match condition setting register (CBR0 or CBR1), the
2. If pre-instruction-execution break is specified for the instruction fetch cycle, the break is
3. If post-instruction-execution break is specified for the instruction fetch cycle, the break is
4. If the instruction fetch cycle is specified as the channel 1 match condition, the DBE bit of
Rev. 2.00 May 22, 2009 Page 1786 of 1982
REJ09B0256-0200
instruction fetch cycle is handled as a match condition. To request a break upon satisfying the
match condition, set the BIE bit in the match operation setting register (CRR0 or CRR1) of the
corresponding channel. Either before or after executing the instruction can be selected as the
break timing according to the PCB bit value. If the instruction fetch cycle is specified as a
match condition, be sure to clear the LSB to 0 in the match address setting register (CAR0 or
CAR1); otherwise, no break occurs.
requested when the instruction is fetched and determined to be executed. Therefore, this
function cannot be used for the instructions which are fetched through overrun (i.e., the
instructions fetched during branching or making transition to the interrupt routine but not
executed). For priorities of pre-instruction-execution break and the other exceptions, refer to
section 5, Exception Handling. If pre-instruction-execution break is specified for the delayed
slot of the delayed branch instruction, the break is requested before the delayed branch
instruction is executed. However, do not specify pre-instruction-execution break for the
delayed slot of the RTE instruction.
requested after the instruction which satisfied the match condition has been executed and
before the next instruction is executed. Similar to pre-instruction-execution break, this
function cannot be used for the instructions which are fetched through overrun. For priorities
of post-instruction-execution break and the other exceptions, refer to section 5, Exception
Handling. If post-instruction-execution break is specified for the delayed branch instruction
and its delayed slot, the break does not occur until the first instruction at the branch
destination.
match condition setting register CBR1 becomes invalid, the settings of match data setting
register CDR1 and match data mask setting register CDMR1 are ignored. Therefore, the data
value cannot be specified for the instruction fetch cycle break.
Instruction Fetch Cycle Break
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