R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 17

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.4 Register Descriptions ......................................................................................................... 417
12.5 Operation ........................................................................................................................... 432
12.6 DDRIF Basic Timing......................................................................................................... 440
Section 13 PCI Controller (PCIC) .....................................................................451
13.1 Features.............................................................................................................................. 451
13.2 Input/Output Pins ............................................................................................................... 454
13.3 Register Descriptions ......................................................................................................... 457
13.4 Operation ........................................................................................................................... 529
12.3.1 Data Alignment..................................................................................................... 414
12.3.2 Data Alignment in Peripheral Modules ................................................................ 416
12.4.1 Memory Interface Mode Register (MIM) ............................................................. 419
12.4.2 DDR-SDRAM Control Register (SCR)................................................................ 423
12.4.3 DDR-SDRAM Timing Register (STR)................................................................. 425
12.4.4 DDR-SDRAM Row Attribute Register (SDR) ..................................................... 428
12.4.5 DDR-SDRAM Mode Register (SDMR) ............................................................... 429
12.4.6 DDR-SDRAM Back-up Register (DBK).............................................................. 431
12.5.1 DDR-SDRAM Access .......................................................................................... 432
12.5.2 DDR-SDRAM Initialization Sequence................................................................. 432
12.5.3 Supported DDR-SDRAM Commands .................................................................. 434
12.5.4 DDR-SDRAM Access Mode................................................................................ 435
12.5.5 Power-Down Modes ............................................................................................. 435
12.5.6 Registers that Set DDR-SDRAM Timing Restrictions ......................................... 436
12.5.7 Operating Frequency............................................................................................. 437
12.5.8 Note on Clock Stop............................................................................................... 437
12.5.9 Using SCR to Issue REFA Commands (Outside the Initialization Sequence)...... 437
12.5.10 Note on Timing of Connected DDR-SDRAM...................................................... 437
12.5.11 Note on Setting Auto-Refresh Interval ................................................................. 438
12.5.12 Address Multiplexing ........................................................................................... 438
12.5.13 DDR-SDRAM Access Arbitration........................................................................ 438
12.5.14 Coherency When Accessing DDR-SDRAM ........................................................ 439
13.3.1 PCIC Enable Control Register (PCIECR) ............................................................ 462
13.3.2 Configuration Registers ........................................................................................ 463
13.3.3 Local Register ....................................................................................................... 488
13.4.1 Supported PCI Commands.................................................................................... 529
13.4.2 PCIC Initialization ................................................................................................ 530
13.4.3 Master Access ....................................................................................................... 531
13.4.4 Target Access........................................................................................................ 539
13.4.5 Host Bus Bridge Mode ......................................................................................... 548
13.4.6 Normal mode ........................................................................................................ 551
Rev. 2.00 May 22, 2009 Page xv of lxviii