R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1701

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When the value in PALDnn[7:3] is 0, 0s should be written to PALDnn[2:0]. Then 8 bits are
extended.
37.4.4
1. Packed 1bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
2. Packed 2bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
3. Packed 4bpp (Pixel Alignment in Byte is Big Endian) [Windows CE Recommended Format]
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Address
+00
+01
+02
+03
…
+LAO+00
+LAO+01
+LAO+02
+LAO+03
…
Data Format
P00
P08
P10
P18
MSB
MSB
MSB
P00
P04
P10
P14
7
7
7
P01 P02 P03 P04 P05 P06 P07
P11 P12 P13 P14 P15 P16 P17
6
6
6
P00
P02
P04
P10
P12
P14
Display Memory
Display Memory
Display Memory
P01
P05
P11
P15
5
5
5
…
…
…
…
…
…
4
4
4
3
3
P02
P06
P12
P16
3
P01
P03
P05
P11
P13
P15
2
2
2
P03
P07
P13
P17
1
1
1
LSB
LSB
LSB
0
0
0
[Bit]
(Byte0)
(Byte1)
[Bit]
(Byte0)
(Byte1)
[Bit]
(Byte0)
(Byte1)
(Byte2)
Rev. 2.00 May 22, 2009 Page 1631 of 1982
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
P00 P01 P02 P03 P04 P05 P06 P07
P10 P11 P12 P13 P14 P15 P16 P17
↓ Top Left Pixel
↓ Top Left Pixel
↓ Top Left Pixel
LAO: Line Address Offset
LAO: Line Address Offset
LAO: Line Address Offset
Section 37 LCD Controller (LCDC)
Pn=Pn[1:0]: Put 2-bit data
Pn=Pn[3:0]: Put 4-bit data
Pn: Put 1-bit data
—Unused bits should be 0
—Unused bits should be 0
—Unused bits should be 0
Display
Display
Display
…
…
…
…
…
…
REJ09B0256-0200
…
…
…
…
…
…