R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 980

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
Note:
23.3.72 Transmit Descriptor List Start Address Register (TDLAR)
TDLAR is a 32-bit readable/writable register that specifies the start address of the transmit
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bits in EDMR. This register must not be modified during transmission.
Modifications to this register should only be made in the transmission-halted state specified by
bits TR[1:0] (= 00) in the E-DMAC transmit request register (EDTRR).
Rev. 2.00 May 22, 2009 Page 910 of 1982
REJ09B0256-0200
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
*
Bit Name
TDLA[31:0]
R/W
R/W
If the receiving function is disabled during frame reception, write-back is not performed
successfully to the receive descriptor. Following pointers to read a receive descriptor
become abnormal and the E-DMAC cannot operate successfully. In this case, to make
E-DMAC reception enabled again, execute a software reset by the SWRT and SWRR
bits in EDMR0 (EDMR1). To disable the E-DMAC receiving function without executing a
software reset, specify the RE bit in ECMR0 (ECMR1). Next, after the E-DMAC has
completed the reception and write-back to the receive descriptor has been confirmed,
disable the receiving function using this register.
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W Description
R/W Transmit Descriptor Start Address
R/W
R/W
26
10
0
0
The lower bits are set according to the specified
descriptor length.
16-byte boundary: TDLA[3:0] = 0000
32-byte boundary: TDLA[4:0] = 00000
64-byte boundary: TDLA[5:0] = 000000
R/W
R/W
25
0
9
0
TDLA[31:15]
R/W
R/W
TDLA[15:0]
24
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0