R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 859

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Name
RMII transmit
data
RMII transmit
data
Transmit clock
Receive clock
Transmit enable
MII/GMII
transmit data
GMII transmit
data
Transmit error
Receive data
valid
MII/GMII receive
data
GMII receive
data
Receive error
Carrier detection
Collision
detection
Management
data clock
Management
data I/O
RMII
management
data clock
Port
0
1
Abbreviation
RMII0_TXD0
RMII0_TXD1
ET1_TX-CLK
ET1_RX-CLK
ET1_TX-EN
ET1_ETXD3 to
ET1_ETXD0
GET1_ETXD7 to
GET1_ETXD4
ET1_TX-ER
ET1_RX-DV
ET1_ERXD3 to
ET1_ERXD0
GET1_ERXD7 to
GET1_ERXD4
ET1_RX-ER
ET1_CRS
ET1_COL
ET1_MDC
ET1_MDIO
RMII1_MDC
I/O
Output
Output
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Output
I/O
Output
Section 23 Gigabit Ethernet Controller (GETHER)
Indicates that transmit data is ready on
Notifies PHY-LSI of error during
Identifies error state occurred during data
Carrier detection signal
Collision detection signal
Reference clock signal for information
Bidirectional signal for exchange of
Reference clock signal for information
Function
2-bit transmit data in RMII mode
2-bit transmit data in RMII mode
ET1_TX-EN, ET1_ETXD3 to
ET1_ETXD0, ET1_TX-ER timing
reference signal
ET1_RX-DV, ET1_ERXD3 to
ET1_ERXD0, ET1_RX-ER timing
reference signal
ET1_ETXD3 to ET1_ETXD0
4-bit MII transmit data or lower four bits of
GMII transmit data
Upper four bits of GMII transmit data
transmission
Indicates that valid receive data is on
ET1_ERXD3 to ET1_ERXD0
4-bit MII receive data or lower four bits of
GMII receive data (MII and GMII)
Upper four bits of GMII receive data
reception
transfer via ET1_MDIO
management information between STA
and PHY
transfer via RMII1_MDIO in RMII mode
Rev. 2.00 May 22, 2009 Page 789 of 1982
REJ09B0256-0200