R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 263

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7.2.2
QACR0 specifies the area onto which store queue 0 (SQ0) is mapped when the MMU is disabled.
Bit
0
Initial value:
Initial value:
Bit
31 to 5
4 to 2
1, 0
R/W:
R/W:
Bit:
Bit:
Queue Address Control Register 0 (QACR0)
Bit Name
OCE
Bit Name

AREA0

31
15
R
R
0
0
30
14
R
R
0
0
29
13
R
R
0
0
Initial
Value
0
Initial
Value
All 0
Undefined R/W
All 0
28
12
R
R
0
0
27
11
R
R
0
0
R/W
R/W
R/W
R
R
26
10
R
R
0
0
Description
OC Enable Bit
Selects whether the OC is used. Note however when
address translation is performed, the OC cannot be
used unless the C bit in the page management
information is also 1.
0: OC not used
1: OC used
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ0.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
25
R
R
0
9
0
24
R
R
0
8
0
23
R
R
0
7
0
Rev. 2.00 May 22, 2009 Page 193 of 1982
22
R
R
0
6
0
21
R
R
0
5
0
R/W
20
R
0
4
AREA0
R/W
19
R
0
3
Section 7 Caches
REJ09B0256-0200
R/W
18
R
2
0
17
R
R
0
1
0
16
R
R
0
0
0