R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 688
R5S77631Y266BGV
Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R5S77631Y266BGV.pdf
(2056 pages)
Specifications of R5S77631Y266BGV
Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 14 Direct Memory Access Controller (DMAC)
The transfer destination is the LBSC space and the DACK and TEND are output during the write
cycle:
(1)
Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or
Tables 14.12 to 14.15 show the number of the bus cycles generated in each DMA transfer and the
register settings for the LBSC space. With these settings, CSn is not negated even if multiple bus
cycles are generated.
Note that, in the following settings, when either the transfer source or the transfer destination is
the LBSC space, to avoid the DACK is asserted ceaselessly during between the two or more times
DMA transfer, set B'001 to B'111 to the IWRRD, IWRRS or IWW bits in CSnBCR. In this
setting, if the 16-byte DMA transfer is performed, multiple bus cycles are generated and the CSn
is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction may
occur.
Rev. 2.00 May 22, 2009 Page 618 of 1982
REJ09B0256-0200
Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR
the transfer destination is the LBSC space and the DACK is output during the write
cycle. And then specifies no idle cycle (CSnBCR.IWRRD, IWRRS, IWW are cleared
to B'000). Note that the case that both the transfer source and the transfer destination
are the LBSC spaces, does not apply this.
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