R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1237

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 28.11 shows an example of the operation for reception in asynchronous mode.
28.4.3
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock
pulses, is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 16-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 28.12 shows the general format for clocked synchronous communication.
Serial data
SCIF_RXD
RDF flag
FER flag
Note: * High except in continuous transfer/reciver.
Synchronization
clock
Serial data
Operation in Clocked Synchronous Mode
Figure 28.12 Data Format in Clocked Synchronous Communication
1
Start
bit
Don't care
0
(Example with 8-Bit Data, Parity, One Stop Bit)
Figure 28.11 Sample SCIF Receive Operation
*
D0
Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
One frame
D1
LSB
Bit 0
Data
Bit 1
One unit of transfer data (character or frame)
D7
RXI interrupt
request
Parity
bit
0/1
Bit 2
Stop
bit
1
Bit 3
Start
bit
0
Data read and RDF flag
read as 1 then cleared to
0 by RXI interrupt handler
Bit 4
D0
Rev. 2.00 May 22, 2009 Page 1167 of 1982
D1
Bit 5
Data
Bit 6
D7
Parity
bit
0/1
Bit 7
MSB
Stop
bit
ERI interrupt request
generated by receive
error
0
Detect flaming
error
Don't care
REJ09B0256-0200
*
0/1