R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1311

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

(6)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.1
used for right-channel data, slot No.2 used for control data for channel 0, slot No.3 used for
control data for channel 1, and frame length = 128 bits
(7)
Synchronous pulse method, falling edge sampling, slot No.0 used for left-channel data, slot No.2
used for right-channel data, slot No.1 used for control data for channel 0 , slot No.3 used for
control data for channel 1, and frame length = 128 bits
SIOF_SCK
SIOF_RXD
SIOF_SYNC
SIOF_TXD
SIOF_SCK
SIOF_SYNC
SIOF_RXD
SIOF_TXD
16-bit Stereo Data (Case 3)
16-bit Stereo Data (Case 4)
Specifications:
Specifications:
Figure 29.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
Figure 29.19 Transmit and Receive Timing (16-Bit Stereo Data (4))
Slot No.0
Slot No.0
L-channel
L-channel
1 bit delay
data
1 bit delay
data
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
TRMD[1:0] = 00 or 10,
TDLE = 1,
RDLE = 1,
CD0E = 1,
Slot No.1
Slot No.1
R-channel
channel 0
Control
data
channel 0
Slot No.2
Slot No.2
R-channel
Control
data
REDG = 0,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] =0010,
REDG = 1,
TDLA[3:0] = 0000,
RDLA[3:0] = 0000,
CD0A[3:0] = 0001,
1 frame
1 frame
Slot No.3
Slot No.3
channel 1
channel 1
Control
Control
Slot No.4
Slot No.4
FL[3:0] = 1110 (frame length: 128 bits),
TDRE = 1,
RDRE = 1,
CD1E = 1,
FL[3:0] = 1110 (frame length: 128 bits)
TDRE = 1,
RDRE = 1,
CD1E = 1,
Rev. 2.00 May 22, 2009 Page 1241 of 1982
Section 29 Serial I/O with FIFO (SIOF)
Slot No.5
Slot No.5
TDRA[3:0] = 0001,
RDRA[3:0] = 0001,
CD1A[3:0] = 0011
TDRA[3:0] = 0010,
RDRA[3:0] = 0010,
CD1A[3:0] = 0011
Slot No.6
Slot No.6
REJ09B0256-0200
Slot No.7
Slot No.7