R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 389

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The local bus state controller (LBSC) divides the external memory space and outputs control
signals corresponding to the specifications of various types of memory and bus interfaces. The
LBSC enables the connection of SRAM or ROM, etc., to this LSI. It also supports the PCMCIA
interface protocol, which is used to implement simplified system design and high-speed data
transfers in a compact system.
11.1
The LBSC has the following features.
• Controls six areas, areas 0 to 2 and 4 to 6, of an external memory space divided into seven
• SRAM interface
• Burst ROM interface
areas.
 Maximum 64 Mbytes for each of areas 0 to 2 and 4 to 6
 Bus width of each area can be controlled through register settings (except area 0, which is
 Wait-cycle insertion by the RDY pin
 Wait-cycle insertion can be controlled by a program
 Types of memory are specifiable for connection to each area
 Output of the control signals of memory to each area
 Automatic wait cycle insertion to prevent data bus collisions on consecutive memory
 Insertion of cycles to ensure the setup time and hold time to the write strobe on a write
 Wait-cycle insertion can be controlled by a program
 Insertion of the wait cycle through the RDY pin
 Wait-cycle insertion can be controlled by a program
 Burst length specified by the register
controlled by the external pin setting)
accesses to different areas, or a read access followed by a write access to the same area
cycle enables connection to low-speed memory
Connectable areas : 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
Connectable areas: 0 to 2 and 4 to 6
Settable bus widths: 32, 16, and 8 bits
Features
Section 11 Local Bus State Controller (LBSC)
Section 11 Local Bus State Controller (LBSC)
Rev. 2.00 May 22, 2009 Page 319 of 1982
REJ09B0256-0200