R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 233

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.3
A TLB load instruction (LDTLB) is provided for recording UTLB entries. When an LDTLB
instruction is issued, this LSI copies the contents of PTEH and PTEL to the UTLB entry indicated
by the URC bit in MMUCR. ITLB entries are not updated by the LDTLB instruction, and
therefore address translation information purged from the UTLB entry may still remain in the
ITLB entry. As the LDTLB instruction changes address translation information, ensure that it is
issued by a program in the P1 or P2 area.
After the LDTLB instruction has been executed, execute one of the following three methods
before an access (include an instruction fetch) the area where TLB is used to translate the address
is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the LT bit in IRMCR is 0 (initial value) before executing the LDTLB instruction, the
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
series.
The operation of the LDTLB instruction is shown in figure 6.11.
area where TLB is used to translate the address.
specific instruction does not need to be executed. However, note that the CPU processing
performance will be lowered because the instruction fetch is performed again for the next
instruction after MMUCR has been updated.
MMU Instruction (LDTLB)
Section 6 Memory Management Unit (MMU)
Rev. 2.00 May 22, 2009 Page 163 of 1982
REJ09B0256-0200