R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1348

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 SIM Card Module (SIM)
(5)
The smart card interface has four types of interrupt requests: transmit data empty interrupt (TXI)
requests, transmit/receive error interrupt (ERI) requests, receive data full interrupt (RXI) requests,
and transmit end interrupt (TEI) requests.
• When the TDRE flag in SCSSR is set to 1, a TXI request is issued.
• When the RDRF flag in SCSSR is set to 1, an RXI request is issued.
• When the ERS, ORER, PER, or WAIT_ER flag in SCSSR is set to 1, an ERI request is issued.
• When the TEND flag in SCSSR is set, a TEI request is issued.
Table 30.6 lists the interrupt sources for the smart card interface. Each of the interrupt requests can
be enabled or disabled using the TIE, RIE, TEIE, and WAIT_IE bits in SCSCR and the EIO bit in
SCSC2R. In addition, each interrupt request can be sent independently to the interrupt controller.
Table 30.6 Interrupt Sources of Smart Card Interface
(6)
The smart card interface enables reception and transmission using the DMAC.
In transmission, when the TDRE flag in SCSSR is set to 1, a DMA transfer request for transmit
data empty is issued. If a DMA transfer request for transmit data empty is set in advance as a
DMAC activation source, the DMAC can be activated and made to transfer data when a DMA
transfer request for transmit data empty occurs.
When in T = 0 mode and if an error signal is received during transmission, the same data is
automatically retransmitted. At the time of this retransmission, no DMA transfer request is issued,
and so the number of bytes specified to the DMAC can be transmitted.
When using the DMAC for transmit data processing and performing error processing as a result of
an interrupt request sent to the CPU, the TIE bit should be cleared to 0 so that no TXI requests are
Rev. 2.00 May 22, 2009 Page 1278 of 1982
REJ09B0256-0200
Transmit mode
Receive mode
Interrupt Operations
Data Transfer Using DMAC
Operating State
Normal operation
Error
Normal operation
Error
Flags
TDRE
TEND
ERS
RDRF
ORER, PER
WAIT_ER
Mask Bits
TIE
TEIE
RIE
RIE
WAIT_IE
RIE, EIO
Interrupt Sources
TXI
TEI
ERI
RXI
ERI
ERI