R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 318

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Interrupt Controller (INTC)
9.3.2
ICR1 is a 32-bit readable/writable register that specifies the individual input signal detection
modes of external interrupt input pins IRQ7/IRL7 to IRQ4/IRL4. This setting is valid only when
using IRL7 to IRL4 and IRL3 to IRL0 as IRQ independent interrupts input to set the IRLM0 and
IRLM1 bits to 1 in ICR0.
Initial value:
Initial value:
Rev. 2.00 May 22, 2009 Page 248 of 1982
REJ09B0256-0200
Bit
22
21 to 0
R/W:
R/W:
Bit:
Bit:
Interrupt Control Register 1 (ICR1)
Bit Name
IRLM1
R/W
31
15
R
0
0
IRQ0S
R/W
30
14
R
0
0
Initial
Value
0
All 0
R/W
29
13
R
0
0
IRQ1S
R/W
28
12
R
0
0
R/W
R/W
R/W
R
27
11
R
0
0
IRQ2S
R/W
26
10
R
0
0
Description
IRL Pin Mode 1
Selects whether IRQ7/IRL7 to IRQ4/IRL4 are used as
the 4-bit encoded interrupt requests or as four
independent interrupts.
0: IRQ7/IRL7 to IRQ4/IRL4 are used as the 4-bit level-
1: IRQ7/IRL7 to IRQ4/IRL4 are used as four
Note: The level-encoded IRL interrupt is not detected
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
25
encoded interrupt requests (IRL [7:4] interrupt; initial
value)
independent interrupt requests (IRQ [n] interrupt; n
= 7 to 4)
R
0
9
0
IRQ3S
unless the pin levels sampled at every bus
clock cycle remain unchanged for four
consecutive cycles.
R/W
24
R
0
8
0
R/W
23
R
0
7
0
IRQ4S
R/W
22
R
0
6
0
R/W
21
R
0
5
0
IRQ5S
R/W
20
R
0
4
0
R/W
19
R
0
3
0
IRQ6S
R/W
18
R
0
2
0
R/W
17
R
0
1
0
IRQ7S
R/W
16
R
0
0
0

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