R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 310

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Interrupt Controller (INTC)
Notes: 1. Since the IRL interrupt request by IRL[3:0] (IRQ3/IRL3 to IRQ0/IRL0 pins) and IRL
9.2
Table 9.2 shows the pin configuration.
Table 9.2
Rev. 2.00 May 22, 2009 Page 240 of 1982
REJ09B0256-0200
On-chip
module
interrupts*
Pin Name
NMI
IRQ3/IRL3 to
IRQ0/IRL0
Source
2. ITI:
3. The SECURITY is not incorporated in the R5S77631A. Therefore, the INTEVT code is
2
Input/Output Pins
interrupt request by IRL[7:4] (IRQ7/IRL7 to IRQ4/IRL4 pins) have the same INTEVT
codes, it is impossible to distinguish the former from the latter. Note that there is no
flags in this LSI for distinguishing between them.
TUNI0 to TUNI5:
TICPI2:
DMINT0 to DMINT11: DMAC channel 0 to 5 transfer end interrupt
DMAE:
ERI0, ERI1:
RXI0, RXI1:
BRI0, BRI1:
TXI0, TXI1:
reserved in the R5S77631A.
GPIO
INTC Pin Configuration
Number of
Sources
(Max.)
4
Function
Nonmaskable interrupt
input pin
External interrupt input pin Input
Priority
Setting value of INT2PRI0
to INT2PRI13
Interval timer interrupt
TMU channel 0 to 5 under flow interrupt
TMU channel 2 input capture interrupt
DMAC address error interrupt (channel 0 to 5)
SCIF channel 0, 1 receive error interrupt
SCIF channel 0, 1 receive data full interrupt
SCIF channel 0, 1 break interrupt
SCIF channel 0, 1 transmission data empty interrupt
I/O
Input
INTEVT
H'F80
H'FA0
H'FC0
H'FE0
Description
Nonmaskable interrupt request
signal input
IRL [3:0] 4-bit level-encoded
interrupt input when ICR0.IRLM0 = 0
IRQ3 to IRQ0 individual interrupt
input when ICR0.IRLM0 = 1
Interrupt request signal input
CH0
CH1
CH2
CH3
Remarks