R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1736

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 38 A/D Converter
ADST
ADF
ADI
Channel 0(AN0)
Channel 1(AN1)
Channel 2(AN2)
Channel 3(AN3)
ADDRA
ADDRB
ADDRC
ADDRD
38.4.2
In multi mode, analog inputs for the specified channels (one or more) are converted once each.
A/D conversion starts with the first channel (AN0) when the ADST bit (bit 13) of the A/D
control/status register (ADCSR) is set to 1 by software.
When multiple channels are selected, A/D conversion for the second channel (AN1) starts
immediately after A/D conversion for the first channel ends.
A/D conversion on the specified channels is performed for one cycle. The conversion results are
transferred for storage to the ADDR that corresponds to the channel.
When setting the A/D control/status register (ADCSR) or switching the analog input channel
during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid
malfunction. After the change has been made, setting the ADST bit to 1 selects the first channel
and A/D conversion is resumed.
Rev. 2.00 May 22, 2009 Page 1666 of 1982
REJ09B0256-0200
Note: * Vertical arrows (↓) indicate instruction execution by software.
Figure 38.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Multi Mode (MDS[1:0] = 10)
Idle
Interrupt occurs
Set*
A/D conversion (1)
Idle
Idle
Idle
Read result
Idle
Clear*
A/D conversion result (1)
A/D conversion (2)
Set*
Read result
Clear*
A/D conversion result (2)
Idle