R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 111

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
31
Notes: 1.
(a) Register configuration
in user mode
Figure 2.2 CPU Register Configuration in Each Processing Mode
2.
3.
4.
R0 _ BANK0*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R0 is used as the index register in indexed register-indirect addressing mode and
indexed GBR indirect addressing mode.
Banked registers
Banked registers
Accessed as general registers when the RB bit is set to 1 in SR. Accessed only by
LDC/STC instructions when the RB bit is cleared to 0.
Banked registers
Accessed as general registers when the RB bit is cleared to 0 in SR. Accessed only
by LDC/STC instructions when the RB bit is set to 1.
MACH
MACL
GBR
R10
R11
R12
R13
R14
R15
SR
PR
PC
R8
R9
1,
2
2
2
2
2
2
2
*
2
0
31
(b) Register configuration in
privileged mode (RB = 1)
R0 _ BANK1*
R0 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
MACH
MACL
GBR
SGR
SSR
VBR
SPC
DBR
R10
R11
R12
R13
R14
R15
PR
SR
PC
R8
R9
1,
1,
*
3
3
3
3
3
3
3
*
4
4
4
4
4
4
4
3
4
0
Rev. 2.00 May 22, 2009 Page 41 of 1982
31
(c) Register configuration in
privileged mode (RB = 0)
Section 2 Programming Model
R0 _ BANK0*
R0 _ BANK1*
R1 _ BANK0*
R2 _ BANK0*
R3 _ BANK0*
R4 _ BANK0*
R5 _ BANK0*
R6 _ BANK0*
R7 _ BANK0*
R1 _ BANK1*
R2 _ BANK1*
R3 _ BANK1*
R4 _ BANK1*
R5 _ BANK1*
R6 _ BANK1*
R7 _ BANK1*
MACH
MACL
GBR
SGR
DBR
SSR
VBR
SPC
R10
R11
R12
R13
R14
R15
PR
R8
R9
SR
PC
1,
1,
*
4
4
4
4
4
4
4
*
3
3
3
3
3
3
3
REJ09B0256-0200
4
3
0

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