R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 888

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.4
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Rev. 2.00 May 22, 2009 Page 818 of 1982
REJ09B0256-0200
Bit
31 to 5
4
3
2
1
0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
E-MAC Interrupt Permission Register (ECSIPR)
Bit Name

PFROIP
PHYIP
LCHNGIP
MPDIP
ICDIP
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
Initial
Value
All 0
0
0
0
0
0
28
12


R
R
0
0
27
11
R/W
R
R/W
R/W
R/W
R/W
R/W


R
R
0
0
26
10

R

R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
PAUSE Frame Retransmit Interrupt Enable
0: Interrupt notification by the PFROI bit is disabled
1: Interrupt notification by the PFROI bit is enabled
ET_PHY-INT Pin Interrupt Enable
0: Interrupt notification by the PHYI bit is disabled
1: Interrupt notification by the PHYI bit is enabled
LINK Signal Change Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
Magic Packet Detect Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
Illegal Carrier Detect Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
25


R
R
0
9
0
24


R
R
0
8
0
23


R
R
0
7
0
22


R
R
0
6
0
21

R

R
0
5
0
PFRO
R/W
20

R
IP
0
4
0
PHYIP
R/W
19

R
0
3
0
LCHN
R/W
GIP
18

R
0
2
0
MPDIP ICDIP
17

R
0
1
0
R/W
16

R
0
0
0