R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 646

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.4
DARB is 32-bit readable/writable registers that specify the destination address of a DMA transfer
that is set in DAR again in repeat/reload mode. Data to be written from the CPU to DAR is also
written to DARB. To set DARB address that differs from DAR address, write data to DARB after
DAR.
To transfer data in word or in longword units, specify the address with word or longword address
boundary. When transferring data in 16-byte or in 32-byte units, a 16-byte or 32-byte boundary
must be set for the source address value. The initial value is undefined.
14.3.5
TCR is 32-bit readable/writable registers that specify the DMA transfer count. The number of
transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper eight bits of TCR are always read as 0, and the write value should always be 0. The
initial value is undefined.
Rev. 2.00 May 22, 2009 Page 576 of 1982
REJ09B0256-0200
Initial value:
Initial value:
Initial value:
Initial value:
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
DMA Destination Address Registers (DARB0 to DARB3)
DMA Transfer Count Registers (TCR0 to TCR5)
R/W
R/W
R/W
R/W
—
—
31
—
15
—
31
15
R/W
R/W
R/W
R/W
30
—
14
—
30
—
14
—
R/W
R/W
R/W
R/W
—
—
29
—
13
—
29
13
R/W
R/W
R/W
R/W
28
—
12
—
28
—
12
—
R/W
R/W
R/W
R/W
27
—
11
—
27
—
11
—
R/W
R/W
R/W
R/W
26
—
10
—
26
—
10
—
R/W
R/W
R/W
R/W
25
—
—
25
—
—
9
9
R/W
R/W
R/W
R/W
—
—
24
—
—
24
8
8
DARB
DARB
TCR
TCR
R/W
R/W
R/W
R/W
23
—
—
23
—
—
7
7
R/W
R/W
R/W
R/W
22
—
—
22
—
—
6
6
R/W
R/W
R/W
R/W
21
—
—
21
—
—
5
5
R/W
R/W
R/W
R/W
20
—
—
20
—
—
4
4
R/W
R/W
R/W
R/W
19
—
—
19
—
—
3
3
R/W
R/W
R/W
R/W
18
—
—
18
—
—
2
2
R/W
R/W
R/W
R/W
17
—
—
17
—
—
1
1
R/W
R/W
R/W
R/W
16
—
—
16
—
—
0
0