R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 205

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.7
(1)
1. Check the BL bit in SR with software. If SPC and SSR have been saved to memory, set the
2. Issue an RTE instruction. When RTE is executed, the SPC contents are saved in PC, the SSR
(2)
1. Exception
2. Interrupt
(3)
1. Re-execution type exception
2. Completion type exception or interrupt
(4)
1. The instruction in the delay slot of the RTE instruction is executed only after the value saved
BL bit in SR to 1 before restoring them.
contents are saved in SR, and branch is made to the SPC address to return from the exception
handling routine.
When an exception other than a user break occurs, a manual reset is executed. The value in
EXPEVT at this time is H'00000020; the SPC and SSR contents are undefined.
If an ordinary interrupt occurs, the interrupt request is held pending and is accepted after the
BL bit in SR has been cleared to 0 by software. If a nonmaskable interrupt (NMI) occurs, it can
be held pending or accepted according to the setting made by software.
In sleep or standby mode, however, an interrupt is accepted even if the BL bit in SR is set to 1.
The PC value for the instruction at which the exception occurred is set in SPC, and the
instruction is re-executed after returning from the exception handling routine. If an exception
occurs in a delay slot instruction, however, the PC value for the delayed branch instruction is
saved in SPC regardless of whether or not the preceding delay slot instruction condition is
satisfied.
The PC value for the instruction following that at which the exception occurred is set in SPC.
If an exception occurs in a branch instruction with delay slot, however, the PC value for the
branch destination is saved in SPC.
in SSR has been restored to SR. The acceptance of the exception related to the instruction
access is determined depending on SR before restoring, while the acceptance of other
exceptions is determined depending on the processing mode by SR after restoring or the BL
Return from exception handling
If an exception or interrupt occurs when BL bit in SR = 1
SPC when an exception occurs
RTE instruction delay slot
Usage Notes
Rev. 2.00 May 22, 2009 Page 135 of 1982
Section 5 Exception Handling
REJ09B0256-0200