R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 500

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 DDR-SDRAM Interface (DDRIF)
Figure 12.3 shows the relationship between write values in SDMR and output signals to the
memory pins.
For example, when the DLL reset release, CAS latency of 2.5 cycles, sequential burst sequence,
and burst length of 2 are set to the mode register in the DDR-SDRAM, the following signals must
be output to the DDR-SDRAM pins.
CS = low, RAS = low, CAS = low, WE = low, BA0 = low, BA1 = low,
MA13/MA12/MA11/MA10/MA9 = low, MA8 = low, MA7 = low, MA6 = high, MA5 = high,
MA4 = low, MA3 = low, MA2 = low, MA1 = low, and MA0 = high
To output the above control signals, write access to address H'FE90 0308 in SDMR is made in
longwords. Then the above control signals are output to the DDR-SDRAM pins. Write data to
SDMR is Don't care.
Rev. 2.00 May 22, 2009 Page 430 of 1982
REJ09B0256-0200
SDRAM
address
L: Low level
H: High level
31
1
30
1
29
Figure 12.3 Relationship between Write Values in SDMR and
1
28
1
27
1
26
1
25
1
24
0
23
1
22
0
Output Signals to Memory Pins
21
0
20
1
19
0
18
0
17
0
16
0
15
0
14
0
13
0
12
0
11
0
10
0
9
1
8
1
7
0
M_CS
M_RAS
M_CAS
M_WE
6
0
5
0
4
0
3
1
2
0
H
H
H
1
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0
0
DDR-SDRAM
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
BA0
BA1
CS
RAS
CAS
WE