R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 12

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.3
5.4
5.5
5.6
5.7
Section 6 Memory Management Unit (MMU).................................................. 137
6.1
6.2
6.3
6.4
6.5
Rev. 2.00 May 22, 2009 Page x of lxviii
Exception Handling Functions........................................................................................... 109
5.3.1
5.3.2
Exception Types and Priorities .......................................................................................... 110
Exception Flow .................................................................................................................. 112
5.5.1
5.5.2
5.5.3
5.5.4
Description of Exceptions.................................................................................................. 116
5.6.1
5.6.2
5.6.3
5.6.4
Usage Notes ....................................................................................................................... 135
Overview of MMU ............................................................................................................ 137
6.1.1
Register Descriptions......................................................................................................... 146
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
TLB Functions ................................................................................................................... 156
6.3.1
6.3.2
6.3.3
MMU Functions................................................................................................................. 162
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
MMU Exceptions............................................................................................................... 166
6.5.1
6.5.2
Exception Handling Flow ..................................................................................... 109
Exception Handling Vector Addresses ................................................................. 109
Exception Flow..................................................................................................... 112
Exception Source Acceptance............................................................................... 114
Exception Requests and BL Bit ............................................................................ 115
Return from Exception Handling.......................................................................... 115
Resets.................................................................................................................... 116
General Exceptions............................................................................................... 118
Interrupts............................................................................................................... 132
Priority Order with Multiple Exceptions .............................................................. 133
Address Spaces ..................................................................................................... 140
Page Table Entry High Register (PTEH).............................................................. 147
Page Table Entry Low Register (PTEL) ............................................................... 148
Translation Table Base Register (TTB) ................................................................ 149
TLB Exception Address Register (TEA) .............................................................. 149
MMU Control Register (MMUCR) ...................................................................... 149
Physical Address Space Control Register (PASCR)............................................. 152
Instruction Re-Fetch Inhibit Control Register (IRMCR) ...................................... 153
Unified TLB (UTLB) Configuration .................................................................... 156
Instruction TLB (ITLB) Configuration................................................................. 159
Address Translation Method................................................................................. 160
MMU Hardware Management.............................................................................. 162
MMU Software Management ............................................................................... 162
MMU Instruction (LDTLB).................................................................................. 163
Hardware ITLB Miss Handling ............................................................................ 164
Avoiding Synonym Problems............................................................................... 165
Instruction TLB Multiple Hit Exception............................................................... 166
Instruction TLB Miss Exception........................................................................... 167