R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1283

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

29.3.10 FIFO Control Register (SIFCTR)
SIFCTR is a 16-bit readable/writable register that indicates the area available for the
transmit/receive FIFO transfer.
Initial value:
Bit
15 to 13 TFWM[2:0]
12 to 8
R/W:
BIt:
Bit Name
TFUA[4:0]
R/W
15
0
TFWM[2:0]
R/W
14
0
R/W
13
0
Initial
Value
000
10000
12
R
1
R/W
R/W
R
11
R
0
TFUA[4:0]
10
R
0
Description
Transmit FIFO Watermark
000: Issue a transfer request when 16 stages of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 12 or more stages
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
•
•
Note: * When the transmit data is DMA-transferred with
Transmit FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (full) to B'10000 (empty).
R
9
0
A transfer request to the transmit FIFO is issued by
the TDREQE bit in SISTR.
The transmit FIFO is always used as 16 stages of
the FIFO regardless of these bit settings.
transmit FIFO are empty.
of the transmit FIFO are empty.
the transmit FIFO are empty.
the transmit FIFO are empty.
transmit FIFO are empty.
the TDMAE bit in the SIIER register set to 1,
the TFWM[2:0] bits should not be set to B'111.
If these bits are set to B'111, a transmit FIFO
overflow may occur.
R
8
0
R/W
7
0
RFWM[2:0]
Rev. 2.00 May 22, 2009 Page 1213 of 1982
R/W
6
0
Section 29 Serial I/O with FIFO (SIOF)
R/W
5
0
R
4
0
R
3
0
RFUA[4:0]
REJ09B0256-0200
R
2
0
R
1
0
R
0
0