R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1378

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Multimedia Card Interface (MMCIF)
31.3.9
CTOCR specifies the period for generating a timeout for the command response.
When the command response is received, CTOCR continues counting the transfer clock and enters
the command timeout error state when the number of transfer clock cycles reaches the number
specified in CTOCR. When the CTERIE bit in INTCR1 is set to 1, the CTERI flag in INTSTR1 is
set. To perform command timeout error handling, the command sequence should be aborted by
setting the CMDOFF bit to 1 and then clearing the CTERI flag.
Note: If an R2 response (17-byte command response) in MMC mode is requested and CTSEL0 is
Rev. 2.00 May 22, 2009 Page 1308 of 1982
REJ09B0256-0200
Bit
7 to 1
0
cleared to 0, a timeout is generated during response reception. Therefore, set CTSEL0 to 1.
Command Timeout Control Register (CTOCR)
Bit Name
—
CTSEL0
Initial value:
Initial
Value
All 0
1
R/W:
Bit:
—
R
7
0
R/W
R
R/W
—
R
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
0: 128 transfer clock cycles from command
1: 256 transfer clock cycles from command
—
R
5
0
transmission completion to response reception
completion
transmission completion to response reception
completion
—
R
4
0
—
R
3
0
—
R
2
0
—
R
1
0
CTSEL0
R/W
0
1