R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 221

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
25, 24
23 to 18
17, 16
15 to 10
9
8
7 to 3
Bit Name

URB

URC
SQMD
SV

Initial
Value
All 0
All 0
All 0
All 0
0
0
All 0
R/W
R
R/W
R
R/W
R/W
R/W
R
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Boundary
These bits indicate the UTLB entry boundary at which
replacement is to be performed. Valid only when URB
≠ 0.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
UTLB Replace Counter
These bits serve as a random counter for indicating
the UTLB entry for which replacement is to be
performed with an LDTLB instruction. This bit is
incremented each time the UTLB is accessed. If URB
> 0, URC is cleared to 0 when the condition URC =
URB is satisfied. Also note that if a value is written to
URC by software which results in the condition of
URC > URB, incrementing is first performed in excess
of URB until URC = H'3F. URC is not incremented by
an LDTLB instruction.
Store Queue Mode Bit
Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception
Single Virtual Memory Mode/Multiple Virtual Memory
Mode Switching Bit
When this bit is changed, ensure that 1 is also written
to the TI bit.
0: Multiple virtual memory mode
1: Single virtual memory mode
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
in case of user access)
Section 6 Memory Management Unit (MMU)
Rev. 2.00 May 22, 2009 Page 151 of 1982
REJ09B0256-0200