R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 406

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Local Bus State Controller (LBSC)
Example:
Modify executing instruction of MMSELR should allocate non-cacheable P2 area and the address
that should not be affected by address map change.
Write to MMSELR before enable Instruction cache, Operand cache, and MMU address translation
and after this never write again until execute power-on reset or manual reset.
11.4.2
The bus control register (BCR) is a 32-bit readable/writable register that specifies the function and
bus cycle status for each area. It is initialized to H'0000 0000 in big-endian mode or H'8000 0000
in little-endian mode by a power-on reset or a mammal reset.
Rev. 2.00 May 22, 2009 Page 336 of 1982
REJ09B0256-0200
Initial value:
Initial value:
-----------------------------------------------------------------------
MOV.L
MOV.L
SYNCO
MOV.L
MOV.L
MOV.L
SYNCO
-----------------------------------------------------------------------
R/W:
R/W:
Bit:
Bit:
Bus Control Register (BCR)
R/W
END
0/1*
IAN
31
15
−
#H'FE600020, R0
#MMSELR_DATA, R1
R1, @R0
R
0
@R0, R2
@R0, R2
R/W
CNT
HIZ
−
30
14
R
0
0
29
13
−
−
R
R
0
0
28
−
12
−
R
R
0
0
27
11
−
−
R
R
0
0
DPUP
R/W
26
10
−
R
0
0
;
; MMSELR_DATA=Writing value of MMSELR
;
; Writing to MMSELR
25
−
−
R
R
0
9
0
OPUP
R/W
24
−
R
0
8
0
R/W
23
−
R
0
7
0
DACKBST[3:0]
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
(upper word=H'A5A5)
R/W
R/W
20
0
4
0
ASYNC[6:0]
R/W
19
−
R
0
3
0
R/W
18
−
R
0
2
0
BREQ
R/W
R/W
17
EN
0
1
0
DMA
R/W
R/W
BST
16
0
0
0