R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 982

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.74 E-MAC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the E-MAC. The information in this register is reported in the form
of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only
bit that is not cleared by writing 1) and are not affected by writing 0. Each interrupt source can
also be masked by means of the corresponding bit in the E-MAC/E-DMAC status interrupt
permission register (EESIPR).
The interrupts generated by this status register are GEINT0 for port 0 and GEINT1 for port 1. For
interrupt priorities, see section 9.4.6, Interrupt Exception Handling and Priority in section 9,
Interrupt Controller (INTC). GEINT2 is an interrupt generated by TSU_FWSR in the TSU.
Rev. 2.00 May 22, 2009 Page 912 of 1982
REJ09B0256-0200
Bit
31, 30
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
TWB[1:0]
R/W
31
15

R
TWB[1:0]
0
0
R/W
30
14

R
0
0
TC[1]
R/W
29
13

R
0
0
Initial
Value
00
R/W
TUC
28
12

R
0
0
R/W
ROC
27
11

R
0
0
R/W
R/W
TABT
R/W
R/W
DLC
26
10
0
0
Description
Write-Back Complete
Indicates that write-back from the E-DMAC to the
corresponding descriptor after frame transmission has
completed. This operation is enabled only when the
TWBI bit in the transmit descriptor that includes the end
of the transmit frame is set to 1.
00: Write-back has not completed, or no transmission
11: Write-back has completed
Others: Setting disabled
RABT RFCOF
R/W
R/W
25
CD
0
9
0
directive
R/W
R/W
TRO
24
0
8
0
RMAF
R/W
23

R
0
7
0
CEEF
R/W
ECI
22
R
0
6
0
TC[0]
CELF
R/W
R/W
21
0
5
0
R/W
R/W
TDE
RRF
20
0
4
0
TFUF
RTLF
R/W
R/W
19
0
3
0
RTSF
R/W
R/W
18
FR
0
2
0
R/W
RDE
PRE
17
0
1
0
CERF
R/W
R/W
RFE
16
0
0
0