R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 490

IC SUPERH MPU ROMLESS 499BGA

R5S77631Y266BGV

Manufacturer Part Number
R5S77631Y266BGV
Description
IC SUPERH MPU ROMLESS 499BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R5S77631Y266BGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
266MHz
Connectivity
Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
107
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
499-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5S77631Y266BGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 420 of 1982
REJ09B0256-0200
Bit
45
44
43 to 35 
34
33
32 to 29 
Bit Name
PCKE
SELFS
RMODE
Initial
Value
0
0
All 0
0
0
All 0
R/W
R
R
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Power Down
When the DDR-SDRAM is not accessed (in the idle
state or bank active state), this bit sets the CKE pin low
and the power-down mode is entered. When this bit is
set to 1, the power-down mode is entered to reduce the
DDR-DSRAM power consumption. For details, see
section 12.5.5, Power-Down Modes. Note that the
setting for enabling the CKE pin by the SMS bit in SCR
is used for DDR-SDRAM initialization.
Reserved
These bits are always read as 0. The write value
should always be 0.
Self-Refresh Decision
Decides whether the DDR-SDRAM is in the self-refresh
state. When this bit is set to 1, the DDR-SDRAM is in
the self-refresh state. When this bit is cleared to 0, the
DDR-SDRAM is not in the self-refresh state.
Refresh Mode Select
Specifies whether auto-refresh mode or self-refresh
mode is set to the DDR-SDRAM. This bit is valid only
when the DRE bit in MIM is set to 1.
0: Auto-refresh mode
1: Self-refresh mode
Reserved
These bits are always read as 0. The write value
should always be 0.

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