R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 621

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The PCIC can store the error information on the PCI bus. If an error occurs, the error address is
stored in the PCI error address information register (PCIAIR), the types of transfer and command
information are stored in the PCI error command information register. And then if the PCIC
operates host bus bridge mode, the bus master information is stored in the PCI error bus master
information register.
Error information is stored only one information. This causes only to store the first occurred error
information, and not to store after second error information. The error information is initialized by
a power-on reset.
13.4.6
When operating in normal mode, the PCI bus arbitration function in the PCIC is disabled and PCI
bus arbitration is performed according to the specifications of the externally connected PCI bus
arbiter.
In normal mode, the master performs bus parking is decided by the grant signal that asserted from
the external bus arbiter. If the master that performing bus parking is different from the next
transaction master, the bus will be high-impedance state for minimum one clock cycle before the
address phase.
In normal mode, the GNT0/GNTIN pin is used for the grant input signal to the PCIC, and the
REQ0/REQOUT pin is used for the request output signal from the PCIC.
13.4.7
The PCIC supports PCI power management revision 1.1. Supported features are shown below.
• Support for the PCI power management control configuration register.
• Support for the power-down/restore request interrupts from hosts on the PCI bus.
There are seven configuration registers for PCI power management control. PCI capabilities
pointer register shows the address offset of the configuration registers for power management. In
the PCIC, this offset is fixed at CP = H'40. PCI capability ID (PCICID), next item pointer
(PCINIP), power management capability (PCIPMC), power management control/status
(PCIPMCSR), PMCSR bridge support extension (PCIPMCSRBSE) and power
consumption/dissipation (PCIPCDD) are power management registers. They support four states:
power state D0 (normal) power state D1 (bus idle) power state D2 (clock stop) and power state D3
(power down mode).
Figure 13.16 shows the PCI local bus power down state transition.
Normal mode
Power Management
Rev. 2.00 May 22, 2009 Page 551 of 1982
Section 13 PCI Controller (PCIC)
REJ09B0256-0200