R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 1370

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Multimedia Card Interface (MMCIF)
31.3.4
A value other than 0 must be written to the TBNCR register if multiple block transfer is selected
by the bits TY5 and TY6 in CMDTYR. Set the transfer block number in TBNCR. Every time a
block transfer ends, the value of TBNCR is decremented by one, and the command sequence
finishes when the TBNCR value reaches 0.
31.3.5
The CMDR registers are six 8-bit registers. A command is written to CMDR as shown in table
31.5, and the command is transmitted when the START bit in CMDSTRT is set to 1.
Table 31.5 CMDR Configuration
Rev. 2.00 May 22, 2009 Page 1300 of 1982
REJ09B0256-0200
Bit
15 to 0
Register
CMDR0
CMDR[1:4]
CMDR5
Initial value:
R/W:
Bit:
TBNCR
Transfer Block Number Counter (TBNCR)
Command Registers 0 to 5 (CMDR0 to CMDR5)
Bit Name
R/W
15
0
Contents
Start bit, Host bit, and
command index
Command argument
CRC and End bits
R/W
14
0
R/W
13
0
Initial
Value
All 0
R/W
12
0
R/W
11
R/W
R/W
0
R/W
10
0
Description
Transfer Block Number Counter
[Clearing condition]
When a specified block number is transferred or 0 is
written to TBNCR.
Operation
Write command index
Set the Start bit to 0 and the Host bit to 1
Write command arguments.
Setting of CRC is unnecessary (automatic calculation).
Setting of the End bit is unnecessary.
R/W
9
0
R/W
8
0
TBNCR
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0