R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 34

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

36.4 Operation ......................................................................................................................... 1561
36.5 EP4 Isochronous-Out Transfer......................................................................................... 1572
36.6 EP5 Isochronous-In Transfer ........................................................................................... 1575
36.7 Processing of USB Standard Commands and Class/Vendor Commands ........................ 1578
36.8 Stall Operations................................................................................................................ 1579
36.9 Examples of External Circuit........................................................................................... 1583
36.10 Usage Notes ..................................................................................................................... 1584
Section 37 LCD Controller (LCDC) ............................................................... 1587
37.1 Features............................................................................................................................ 1587
37.2 Input/Output Pins............................................................................................................. 1589
37.3 Register Configuration..................................................................................................... 1590
Rev. 2.00 May 22, 2009 Page xxxii of lxviii
36.3.35 Time Stamp Register (TSRH/TSRL).................................................................. 1546
36.3.36 Control Register 0 (CTLR0) ............................................................................... 1548
36.3.37 Control Register 1 (CTLR1) ............................................................................... 1550
36.3.38 Endpoint Information Register (EPIR) ............................................................... 1551
36.3.39 Timer Register (TMRH/TMRL) ......................................................................... 1557
36.3.40 Set Time Out Register (STOH/STOL) ............................................................... 1559
36.4.1 Cable Connection................................................................................................ 1561
36.4.2 Cable Disconnection ........................................................................................... 1562
36.4.3 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................. 1568
36.4.4 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................... 1569
36.4.5 EP3 Interrupt-In Transfer.................................................................................... 1571
36.7.1 Processing of Commands Transmitted by Control Transfer............................... 1578
36.8.1 Overview ............................................................................................................ 1579
36.8.2 Forcible Stall by Application .............................................................................. 1579
36.8.3 Automatic Stall by USB Function Controller ..................................................... 1581
36.9.1 Example of the Connection between USB Function Controller ......................... 1583
36.10.1 Setup Data Reception ......................................................................................... 1584
36.10.2 FIFO Clear.......................................................................................................... 1584
36.10.3 Overreading/Overwriting of Data Register......................................................... 1584
36.10.4 Assigning EP0 Interrupt Sources ........................................................................ 1585
36.10.5 FIFO Clear when DMA Transfer is Set .............................................................. 1585
36.10.6 Note on Using TR Interrupt ................................................................................ 1585
37.3.1 LCDC Input Clock Register (LDICKR) ............................................................. 1593
37.3.2 LCDC Module Type Register (LDMTR) ........................................................... 1595
37.3.3 LCDC Data Format Register (LDDFR).............................................................. 1598
37.3.4 LCDC Scan Mode Register (LDSMR) ............................................................... 1600
37.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ......... 1601
37.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ......... 1603