R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 497

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
10 to 8
7 to 5
4 to 2
Bit Name
SRAS
SRC
SCL
Initial
Value
000
000
000
R/W
R/W
R/W
R/W
Description
Minimum Number of Cycles between ACT and PRE
Commands
These bits specify the minimum number of cycles from
ACT command issuance to PRE command issuance in
the same bank (Tras).
000: 6 cycles
001: 7 cycles
010: 8 cycles
011: 9 cycles
Other than above: Setting prohibited
Auto-Refresh/ACT Command Issuance Cycle
These bits specify the number of cycles in the same
bank for the following access times (Trc).
(1) From ACT command issuance to auto refresh
(2) From ACT command issuance to ACT command
issuance
000: 6 cycles
001: 7 cycles
010: 8 cycles
011: 9 cycles
100: 10 cycles
101: 11 cycles
110: 12 cycles
111: 13 cycles
Other than above: Setting prohibited
CAS Latency
These bits specify the CAS latency (CL) in data read.
000: 2.5 cycles
The write value should always be 0.
Section 12 DDR-SDRAM Interface (DDRIF)
Rev. 2.00 May 22, 2009 Page 427 of 1982
REJ09B0256-0200