R5S77631Y266BGV Renesas Electronics America, R5S77631Y266BGV Datasheet - Page 508

• Manufacturer Part Number: R5S77631Y266BGV
• Description: IC SUPERH MPU ROMLESS 499BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R5S77631Y266BGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 266MHz
• Connectivity: Audio Codec, I²C, MMC, SCI, SIM, SIO, SSI, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 107
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 499-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.5.11 Note on Setting Auto-Refresh Interval
The auto-refresh interval is specified by the DRI bits in MIM. If the DRE bit is set to 1 at the same
time as the DRI bits are set, the time until the first auto-refresh is that selected by the value of the
DRI bits before the new setting was made. However, the second and subsequent auto-refresh
intervals take on the value corresponding to the new setting for the DRI bits. To avoid this
situation, clear the DRE bit to 0 when setting the DRI bits. When the DRE bit is subsequently set
to 1, auto-refreshing proceeds with the specified interval from the first round. When writing 1 to
the DRE bit, the previously written cycle number should be set to the DRI bits.
12.5.12 Address Multiplexing
Address multiplexing is performed so that the DDR-SDRAM is connected without the external
address multiplexing circuit according to the setting of the BW bits in MIM and the SPLIT bits in
SDR. Table 12.7 shows the relationship between the DDR-SDRAM bus width and the addresses
that are output to the address pins according to the setting of the SPLIT bits. If a setting not
specified in table 12.7 is used, correct operation is not guaranteed.
Table 12.7 DDR-SDRAM Address Multiplexing (32-Bit Data Bus)
Note:
12.5.13 DDR-SDRAM Access Arbitration
(1)
The DDRIF has the access arbitration function that arbitrates accesses to the DDR-SDRAM
between the CPU and the LCDC. The priority order of the arbitration is divided in the following
two levels.
Rev. 2.00 May 22, 2009 Page 438 of 1982
REJ09B0256-0200
128 M bits × 2
(8 M × 16-bit × 2)
256 M bits × 2
(16 M × 16-bit × 2)
512 M bits × 2
(32 M × 16-bit × 2)
1 G bits × 2
(64 M × 16-bit × 2)
Priority Order of Access Arbitration
*
Auto-precharge
SPLIT[3:0] ROW × COL
0001
0011
0100
0110
12 × 9
13 × 9
13 × 10
14 × 10
ROW
COL
ROW
COL
ROW
COL
ROW
COL
M_
BA1
13
13
13
13
13
13
13
13
M_
BA0
12
12
12
12
12
12
12
12
M_
A13
27
—
—
—
—
—
—
—
M_
A12
11
26
26
—
—
—
—
—
M_
A11
11
25
25
25
— AP* —
— AP* —
— AP* 11
— AP* 11
M_
A10
24
24
24
24
M_
A9
23
23
23
23
M_
A8
22
10
22
10
22
10
22
10
M_
A7
21
21
21
21
9
9
9
9
M_
A6
20
20
20
20
8
8
8
8
M_
A5
19
19
19
19
7
7
7
7
M_
A4
18
18
18
18
6
6
6
6
M_
A3
17
17
17
17
5
5
5
5
M_
A2
16
16
16
16
4
4
4
4
M_
A1
15
15
15
15
3
3
3
3
M_
A0
14
14
14
14
2
2
2
2