LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 100

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 76.
Base clock
BASE_APB1_CLK CLK_APB1_BUS
BASE_SPIFI_CLK CLK_SPIFI
BASE_M3_CLK
CCU1 branch clocks
All information provided in this document is subject to legal disclaimers.
Branch clock
CLK_APB3_ADC0
CLK_APB3_ADC1
CLK_APB3_CAN0
CLK_APB1_MOTOCON
CLK_APB1_I2C0
CLK_APB1_I2S
CLK_APB1_CAN1
CLK_M3_BUS
CLK_M3_SPIFI
CLK_M3_GPIO
CLK_M3_LCD
CLK_M3_ETHERNET
CLK_M3_USB0
CLK_M3_EMC
CLK_M3_SDIO
CLK_M3_DMA
CLK_M3_M3CORE
CLK_M3_AES
CLK_M3_SCT
CLK_M3_USB1
CLK_M3_EMC_DIV
CLK_M3_VADC
CLK_M3_WWDT
CLK_M3_UART0
CLK_M3_UART1
CLK_M3_SSP0
CLK_M3_TIMER0
CLK_M3_TIMER1
CLK_M3_SCU
CLK_M3_CREG
CLK_M3_RITIMER
Rev. 00.13 — 20 July 2011
Chapter 10: LPC18xx Clock Control Unit (CCU)
Description
Clock to the ADC0 register interface and ADC0
peripheral clock.
Clock to the ADC1 register interface and ADC1
peripheral clock.
Clock to the C_CAN0 register interface and
C_CAN0 peripheral clock.
Clock to the PWM Motor control block and PWM
Motocon peripheral clock.
peripheral clock.
Clock to the I2S0 and I2S1 register interfaces
and I2S0 and I2S1 peripheral clock.
Clock to the C_CAN1 register interface and
C_CAN1 peripheral clock.
clock for the SPIFI SCKI clock input.
Clock to the GPIO register interface
Clock to the Ethernet register interface.
Clock to the USB0 register interface.
Clock to the External memory controller.
Clock to the SD/MMC register interface.
Clock to the Cortex-M3 core
Clock to the AES register interface.
Clock to the USB1 register interface.
Clock to the EMC with clock divider.
Clock to the VADC.
Clock to the USART0 register interface.
Clock to the timer0 register interface and timer0
peripheral clock.
Clock to the timer1 register interface and timer1
peripheral clock.
Clock to the System control unit register
interface.
timer peripheral clock.
APB1 bus clock.
Clock to the I2C0 register interface and I2C0
M3 bus clock.
Clock to the SPIFI register interface.
Clock to the LCD register interface.
Clock to the DMA register interface.
Clock to the SCT register interface.
Clock to the WWDT register interface.
Clock to the UART1 register interface.
Clock to the SSP0 register interface.
Clock to the CREG register interface.
Clock to the RI timer register interface and RI
UM10430
© NXP B.V. 2011. All rights reserved.
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