LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 589
LPC1837FET256,551
Manufacturer Part Number
LPC1837FET256,551
Description
Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1837FET256,551
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Details
Other names
935293795551
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24.5 Pin description
24.6 Register description
<Document ID>
User manual
Table 498. SCT pin description
The register addresses of the State Configurable Timer are shown in
of the SCT registers, the register function depends on the setting of certain other register
bits:
Function name
CTIN_[7:0]
CTOUT_[15:0]
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
2. The REGMODEn bits in the REGMODE register determine whether each set of
Fig 63. SCT counter and select logic
CLK_M3_SCT
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: The L and H registers can be accessed by a 32-bit read or write
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
Match/Capture registers uses the match or capture functionality:
– REGMODEn = 1: Registers operate as match and reload registers.
operation or can be read or written to individually (for operation as two 16-bit
counter/timers).
All information provided in this document is subject to legal disclaimers.
Direction
I
O
Rev. 00.13 — 20 July 2011
Description
State Configurable Timer (SCT) inputs.
State Configurable Timer (SCT) outputs.
Chapter 24: LPC18xx State Configurable Timer (SCT)
prescaler
prescaler
SCT clock
Table
UM10430
H counter
L counter
© NXP B.V. 2011. All rights reserved.
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