LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1005

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.5.2 Basic configuration
42.5.3 Features
42.5.4 General description
The CCU1/2 are configured as follows:
Table 951. CCU clocking and power control
The CCUs switch the clocks to individual peripherals on or off.
Each CGU base clock has several clock branches which can be turned on or off
independently by the Clock Control Units CCU1 or CCU2. The branch clocks are
distributed between CCU1 and CCU2.
Table 952. CCU1 branch clocks
CCU1
CCU2
Base clock
BASE_APB3_CLK CLK_APB3_BUS
BASE_APB1_CLK CLK_APB1_BUS
BASE_SPIFI_CLK CLK_SPIFI
•
•
•
•
See
Do not reset the CCUs during normal operation.
Auto mode activates the AHB disable protocol before switching off the branch clock.
Wake-up mode allows to select clocks to run automatically after a wake-up event.
Table 951
Base clock
BASE_M3_CLK
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Branch clock
CLK_APB3_I2C1
CLK_APB3_DAC
CLK_APB3_ADC0
CLK_APB3_ADC1
CLK_APB3_CAN
CLK_APB1_MOTOCON
CLK_APB1_I2C0
CLK_APB1_I2S
Rev. 00.13 — 20 July 2011
Branch clock
CLK_M3_BUS
CLK_M3_BUS
Description
peripheral clock.
Clock to the DAC register interface.
Clock to the ADC0 register interface and ADC0
peripheral clock.
Clock to the ADC1 register interface and ADC1
peripheral clock.
Clock to the C_CAN register interface and
C_CAN peripheral clock.
Clock to the PWM Motor control block and PWM
Motocon peripheral clock.
peripheral clock.
Clock to the I2S register interface and I2S
peripheral clock.
Clock to the I2C1 register interface and I2C1
Clock to the I2C0 register interface and I2C0
clock for the SPIFI SCKI clock input.
Chapter 42: Appendix
Maximum frequency
150 MHz
150 MHz
UM10430
© NXP B.V. 2011. All rights reserved.
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