LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 375

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 317. USB Periodic List Base register in host mode (PERIODICLISTBASE - address 0x4000 6154) bit
Table 318. USB Endpoint List Address register in device mode (ENDPOINTLISTADDR - address 0x4000 6158) bit
Table 319. USB Asynchronous List Address register in host mode (ASYNCLISTADDR- address 0x4000 6158) bit
<Document ID>
User manual
Bit
11:0
31:12
Bit
10:0
31:11
Bit
4:0
31:5
Symbol
-
EPBASE31_11
Symbol
-
ASYBASE31_5
Symbol
-
PERBASE31_12
description
description
description
20.6.8.1 Device mode
20.6.8.2 Host mode
20.6.9.1 Device mode
20.6.8 Endpoint List Address register (ENDPOINTLISTADDR - device) and
20.6.9 TT Control register (TTCTRL)
physical memory pointer is assumed to be 4 kB aligned. The contents of this register are
combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step
through the Periodic Frame List in sequence.
Asynchronous List Address (ASYNCLISTADDR - host) registers
In device mode, this register contains the address of the top of the endpoint list in system
memory. Bits[10:0] of this register cannot be modified by the system software and will
always return a zero when read.The memory structure referenced by this physical
memory pointer is assumed 64 byte aligned.
This 32-bit register contains the address of the next asynchronous queue head to be
executed by the host. Bits [4:0] of this register cannot be modified by the system software
and will always return a zero when read.
This register is not used in device mode.
Description
reserved
Endpoint list pointer (low)
These bits correspond to memory address signals 31:11, respectively. This
field will reference a list of up to 4 Queue Heads (QH). (i.e. one queue head
per endpoint and direction.)
Description
Reserved
Link pointer (Low) LPL
These bits correspond to memory address signals 31:5, respectively. This
field may only reference a Queue Head (OH).
Description
Reserved
Base Address (Low)
These bits correspond to the memory address signals 31:12.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
Reset
value
0
-
Reset
value
-
-
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Access
-
R/W
Access
-
R/W
Access
-
R/W