LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 903

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 829. A/D Control register (CR - address 0x400E 3000 (ADC0) and 0x400E 4000 (ADC1)) bit description
<Document ID>
User manual
Bit
27
31:28 -
Symbol
EDGE
38.6.2 A/D Global Data register
38.6.3 A/D Interrupt Enable register
Value
0
1
-
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
Table 830. A/D Global Data register (GDR - address 0x400E 3004 (ADC0) and 0x400E 4004
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Bit
5:0
15:6
23:16 -
26:24 CHN
29:27 -
30
31
Symbol
-
V_VREF
OVERRUN
DONE
Description
This bit is significant only when the START field contains 0x2 -0x6. In these
cases:
Start conversion on a rising edge on the selected signal.
Start conversion on a falling edge on the selected signal.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
(ADC1)) bit description
All information provided in this document is subject to legal disclaimers.
Description
Reserved. These bits always read as zeroes.
When DONE is 1, this field contains a binary fraction representing
the voltage on the ADCn pin selected by the SEL field, divided by
the reference voltage on the VDDA pin. Zero in the field indicates
that the voltage on the ADCn input pin was less than, equal to, or
close to that on VSSA, while 0x3FF indicates that the voltage on
ADCn input pin was close to, equal to, or greater than that on
VDDA.
Reserved. These bits always read as zeroes.
These bits contain the channel from which the LS bits were
converted.
Reserved. These bits always read as zeroes.
This bit is 1 in burst mode if the results of one or more conversions
was (were) lost and overwritten before the conversion that
produced the result in the V_VREF bits.
This bit is set to 1 when an analog-to-digital conversion completes.
It is cleared when this register is read and when the AD0/1CR
register is written. If the AD0/1CR is written while a conversion is
still in progress, this bit is set and a new conversion is started.
Rev. 00.13 — 20 July 2011
Chapter 38: LPC18xx 10-bit ADC0/1
UM10430
© NXP B.V. 2011. All rights reserved.
903 of 1164
Reset
value
0
-
Reset
value
0
-
0
-
0
0
0