LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1057

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
42.8.4.2 GPIO port mask register (MASK)
Table 982. GPIO port direction control byte and halfword accessible register view
This register is used to select port pins that will and will not be affected by write accesses
to the SET, CLR, and PIN register. The mask register also filters out the port’s content
when the PIN register is read and masks the contents of the SET register for read
operations.
A zero in this register’s bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, the corresponding pin will not be changed
with write access and if read, will not be reflected in the updated PIN register.
Reading returns the status of the MASK register.
Table 983. GPIO port mask register (MASK0 to MASK4 - addresses 0x400F 0010 to 0x400F
Aside from the 32-bit long and word only accessible MASKn register, every GPIO port can
also be controlled via two byte and one half-word accessible register listed in
Next to providing the same functions as the MASKn register, these additional registers
allow easier and faster access to the physical port pins.
Generic
register
name
DIRn_0
DIRn_1
DIRn_L
Bit
15:0
31:16 -
Symbol
MASKPIN
0090) bit description
Description
GPIO port x (x = 0 to 4)
direction control register 0. Bit
0 corresponds to pin
GPIOx_0... bit 7 to pin
GPIOx_7.
GPIO port x direction control
register 1. Bit 0 corresponds to
pin GPIOx_8... bit 7 to pin
GPIOx_15.
GPIO port x direction control
Lower half-word register. Bit 0
corresponds to pin GPIOx_0...
bit 15 to pin GPIOx_15.
All information provided in this document is subject to legal disclaimers.
Description
GPIO physical pin access control. Bit 0 controls pin GPIOx_0, bit
15 controls pin GPIOx_15.
0 = Controlled pin is affected by writes to the port’s SETn, CLRn,
and PINn register(s). Current state of the pin can be read from the
PINn register.
1 = Controlled pin is not affected by writes into the port’s SETn,
CLRn and PINn register(s). When the PIN register is read, this bit
will not be updated with the state of the physical pin.
Reserved.
Rev. 00.13 — 20 July 2011
Register
length in bits
/access
8 (byte)/
R/W
8 (byte)/
R/W
16
(half-word)/
R/W
Reset
value
0x00
0x00
0x0000 DIR0_L - 0x400F 0000
Port x register name -
address
DIR0_0 - 0x400F 0000
DIR1_0 - 0x400F 0020
DIR2_0 - 0x400F 0040
DIR3_0 - 0x400F 0060
DIR4_0 - 0x00FF 0080
DIR0_1 - 0x400F 0001
DIR1_1 - 0x400F 0021
DIR2_1 - 0x400F 0041
DIR3_1 - 0x400F 0061
DIR4_1 - 0x400F 0081
DIR1_L - 0x400F 0020
DIR2_L - 0x400F 0040
DIR3_L - 0x400F 0060
DIR4_L - 0x400F 0080
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Table
1057 of 1164
Reset
value
0x0
-
984.