LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 328

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.2 EMC Status register
Table 266. EMC Control register (CONTROL - address 0x4000 5000) bit description
[1]
The read-only Status register provides EMC status information.
Table 267. EMC Status register (STATUS - address 0x4000 5008) bit description
Bit
0
1
2
31:3
Bit
0
1
The external memory cannot be accessed in low-power or disabled state. If a memory access is performed
an AHB error response is generated. The EMC registers can be programmed in low-power and/or disabled
state.
Symbol
Symbol
-
B
S
E
M
L
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
Value Description
0
1
0
1
0
1
-
Rev. 00.13 — 20 July 2011
EMC Enable. Indicates if the EMC is enabled or
disabled.Disabling the EMC reduces power consumption. When
the memory controller is disabled the memory is not refreshed.
The memory controller is enabled by setting the enable bit, or by
reset. This bit must only be modified when the EMC is in idle
state.
Disabled
Enabled (POR and warm reset value).
Address mirror. Indicates normal or reset memory map. On POR,
CS1 is mirrored to both CS0 and DYCS0 memory areas.
Clearing the M bit enables CS0 and DYCS0 memory to be
accessed.
Normal memory map.
Reset memory map. Static memory CS1 is mirrored onto CS0
and DYCS0 (POR reset value).
Low-power mode. Indicates normal, or low-power mode.
Entering low-power mode reduces memory controller power
consumption. Dynamic memory is refreshed as necessary. The
memory controller returns to normal functional mode by clearing
the low-power mode bit (L), or by POR.
This bit must only be modified when the EMC is in idle state.
Normal mode (warm reset value).
Low-power mode.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Busy.
This bit is used to ensure that the memory controller enters
the low-power or disabled mode cleanly by determining if
the memory controller is busy or not:
EMC is idle (warm reset value).
EMC is busy performing memory transactions, commands,
auto-refresh cycles, or is in self-refresh mode (POR reset
value).
Write buffer status. This bit enables the EMC to enter
low-power mode or disabled mode cleanly:
Write buffers empty (POR reset value)
Write buffers contain data.
[1]
Chapter 19: LPC18xx External Memory Controller (EMC)
UM10430
© NXP B.V. 2011. All rights reserved.
[1]
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Reset
value
1
0
Reset
value
1
1
0
-